PIC32CX-BZ6_DFP

        - Corrected OTP-page access permissions and eFuse UUID offsets for PIC32CX2051BZ62132, PIC32CX2051BZ66048, PIC32WM_BZ6204, and PIC32WM_BZ6602.
        - Added PATCH_LCK secure-configuration fuse definitions for PIC32CX-BZ6 and PIC32WM-BZ6 devices.
        - Fixed generated XC32/XC Arm Clang startup CALL_MAIN behavior, including stack alignment and compiler-visible register clobbers.
        - Placed GCC exception-unwind metadata in executable memory sections.
        - Fixed GCC linker-script TLS .tbss reservation for picolibc thread-local storage.
        - Updated XC32 target options to explicitly select Cortex-M4 without DSP extensions.
        - Updated Keil flash algorithms.
        - *** Note: XC32 startup sources no longer define the weak SystemInit function or SystemCoreClock variable. ***

        - Added CMSIS flash loaders for Keil and pyOCD.
        - CMSIS System Initialization is now included as default. Define DISABLE_CMSIS_INIT to not include.
        - Interrupt handler in startup_(device).c changed: SVCall_Handler -> SVC_Handler and NonMaskableInt_Handler -> NMI_Handler.

                - Added ARMCC scatter/linker script
                - Added WBZ653.

                - Changed bitfield names of CFGPCLKGEN1-4.
                - Modified register name from DAC_CODE to DACCODE.
                - Correded the DAC_CTRL id.
                - Removed WBZ653.

                - Added PIC32WM_BZ6204.
                - Updated CNCON bits in GPIO.
                - Updated PAC, QEI, FUSE, CFG, and SERCOM.

Initial release.