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  1. Packs
  2. PIC32CK-SG_DFP

Change Log

Version 1.10.278: Sept. 8, 2026

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        - Added an explicit .noinit (NOLOAD) output section to the GCC linker scripts and ARM Compiler (armcc) scatter files for all devices, so that variables placed in .noinit no longer cause objcopy binary output to be padded with the address gap between flash and RAM (DEVXML-8441).

Version 1.9.276: Sept. 7, 2026

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        - Removed unused placeholder interrupt vector entries (ADC Reserved2-5, CAN0/CAN1 Reserved6/7, ETH, HSM Error/RX/TX, and index 154 Reserved) from PIC32CK-SG00 devices, which do not implement CAN, Ethernet, or Hardware Security Module peripherals.
        - Removed non-existent QOS4 bitfield from the DMA CTRLB register.
        - Split the shared CCL LUTCTRL INSEL bitfield into per-input INSEL0, INSEL1, and INSEL2 value groups.
        - Corrected ARM Cortex-M33 core module register definitions: removed MMFSR, BFSR, and UFSR (now represented only via CFSR), removed unimplemented auxiliary and peripheral ID registers, and corrected Debug Authentication Status Register bitfield and value-group naming.
        - Removed unimplemented Battery Backup Power Switch (BBPS), secondary I/O bank (VDDIOB) BOR, and eMMC/SD Host Controller extended-capability bitfields.
        - Corrected missing ADC and EIC pin signals, incorrect ADC channel-configuration bitfield masks, and removed nonexistent bitfields for PIC32CK1012SG00048.
        - Fixed missing source ATDF files for PIC32CK1012SG00 devices, correcting their generated XC32 configuration data.
        - Renamed TZ1_CE_Keyword0-3 debug variables to CE_Keyword0-3 in the PDSC and Keil debug configuration.
        - Updated header macros to use explicit (uint32_t) casts in value-to-mask assignments.

Version 1.8.265: Aug. 19, 2026

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        - Fixed overlapping and missing bitfields in the CoreDebug DHCSR register for Cortex-M33 devices.
        - Removed incorrectly generated non-secure FPU instance header (fpu_ns.h).
        - Added additional linker script variants for alternative memory configurations (PFM flash, CMCC data RAM, EBI chip select, HSRAM retention).
        - Added Keil MDK-ARM toolchain support (flash loaders, debug configuration, and CMSIS-Toolbox csolution/cproject project templates).

Version 1.7.233: Feb. 9, 2026

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        - Added CMSIS flash loaders.
        - Added TrustZone project template.

Version 1.6.199: July 15, 2025

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        - Enabled ICD4/5 and ICE4 to also support PIC32CK1012SG01048, PIC32CK1012SG01064, PIC32CK1012SG01100.

Version 1.5.191: April 23, 2025

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        - Added PIC32CK1012SG00048, PIC32CK1012SG01048, PIC32CK1012SG00064, PIC32CK1012SG01064, PIC32CK1012SG00100, and PIC32CK1012SG01100.

Version 1.4.190: April 15, 2025

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          - Added ARMCC scatter/linker script.
          - Added PIC32CK1025SG00144, and PIC32CK1025SG01144.
          - Removed USBHS module descriptor.
          - Added BSDAP module descriptor.

Version 1.3.168: April 23, 2024

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        - Added missing FUSE bitfield for EBI security attribute (MH3-91330).

Version 1.2.161: Nov. 28, 2023

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          - Defined STIR register
          - Updated FUCFG11 and FUCFG12 registers bitfield for PIC32CK_SG FUSES.
          - Updated header file license to Apache 2.0.

Version 1.1.156: Aug. 2, 2023

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          - Updated linkerscripts VECTOR_REGION to boot_rom.
          - Fixed interrupt naming for reserved vectors.

Version 1.0.141: April 5, 2023

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Initial release.