MIMXRT1180-EVK
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Cores
Cortex-M7
Cortex-M33
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Device
MIMXRT1189CVM8B -
CMSIS Pack
MIMXRT1180-EVK_BSP
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asrc_m2m_polling_cm7
µVision AC6The asrc_m2m_polling example shows how to use asrc driver with polling:In this example, one sai instance playbacks the audio data conveted by asrc.
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asrc_m2m_polling_cm7
Keil Studio AC6, GCC, IARThe asrc_m2m_polling example shows how to use asrc driver with polling:In this example, one sai instance playbacks the audio data conveted by asrc.
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bubble_peripheral_cm33
µVision AC6The bubble level demo demonstrates basic usage of the on-board accelerometer to implement a bubble level. A bubble level utilizes two axes to visually show deviation from a level plane (0 degrees) on a given axis. You can open the mex file with MCUXpresso Config Tool to do further configuration of pin, clock and peripheral.
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bubble_peripheral_cm33
Keil Studio AC6, GCC, IARThe bubble level demo demonstrates basic usage of the on-board accelerometer to implement a bubble level. A bubble level utilizes two axes to visually show deviation from a level plane (0 degrees) on a given axis. You can open the mex file with MCUXpresso Config Tool to do further configuration of pin, clock and peripheral.
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bubble_peripheral_cm7
µVision AC6The bubble level demo demonstrates basic usage of the on-board accelerometer to implement a bubble level. A bubble level utilizes two axes to visually show deviation from a level plane (0 degrees) on a given axis. You can open the mex file with MCUXpresso Config Tool to do further configuration of pin, clock and peripheral.
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bubble_peripheral_cm7
Keil Studio AC6, GCC, IARThe bubble level demo demonstrates basic usage of the on-board accelerometer to implement a bubble level. A bubble level utilizes two axes to visually show deviation from a level plane (0 degrees) on a given axis. You can open the mex file with MCUXpresso Config Tool to do further configuration of pin, clock and peripheral.
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cache_cm33
µVision AC6The cache example shows how to use memory cache driver.In this example, many memory (such as SDRAM, etc) and DMA will be used to show the example.Those memory is both accessible for cpu and DMA. For the memory data alignment, cache driver should be used rightly. For cache enabled case, the cache invalidate operation should be done before cpu access the memory. The cache clean opeartion should be done after CPU verify the memorymemory and before DMA access the memory.
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cache_cm33
Keil Studio AC6, GCC, IARThe cache example shows how to use memory cache driver.In this example, many memory (such as SDRAM, etc) and DMA will be used to show the example.Those memory is both accessible for cpu and DMA. For the memory data alignment, cache driver should be used rightly. For cache enabled case, the cache invalidate operation should be done before cpu access the memory. The cache clean opeartion should be done after CPU verify the memorymemory and before DMA access the memory.
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cache_cm7
Keil Studio AC6, GCC, IARThe cache example shows how to use memory cache driver.In this example, many memory (such as SDRAM, etc) and DMA will be used to show the example.Those memory is both accessible for cpu and DMA. For the memory data alignment, cache driver should be used rightly. For cache enabled case, the cache invalidate operation should be done before cpu access the memory. The cache clean opeartion should be done after CPU verify the memorymemory and before DMA access the memory.
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cache_cm7
µVision AC6The cache example shows how to use memory cache driver.In this example, many memory (such as SDRAM, etc) and DMA will be used to show the example.Those memory is both accessible for cpu and DMA. For the memory data alignment, cache driver should be used rightly. For cache enabled case, the cache invalidate operation should be done before cpu access the memory. The cache clean opeartion should be done after CPU verify the memorymemory and before DMA access the memory.
Download Pack