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  1. Devices
  2. BMP Series
  3. BMP
  4. BMP561

BMP561

Geehy

  • Core

    Cortex-M0+, 4 MHz

  • Family

    BMP Series

  • Sub-Family

    BMP

  • CMSIS Pack

    BMP561_DFP

Geehy Semiconductor' BMP561 based on ARM Cortex'-M0+ core.
Core
- ARM 32-bit Cortex-M0+ CPU
Memories
- 64 Kbytes of Main Flash memory
- 4 Kbytes of Data Flash memory
- 8 Kbytes of SRAM
Reset and power management
- Power-on/Power down reset (POR/PDR)
- Low power modes: Wait, Sleep, Deep sleep, Hibernate
Clock management
- 1 to 16 MHz high frequency oscillator
- 65 kHz low frequency oscillator

Core

Processor

Cortex-M0+
Maximum Clock Frequency 4 MHz
Memory Protection Unit NO_MPU
Floating Point Unit NO_FPU
Trust Zone
Digital Signal Processor
CortexM Vector Extensions
Endian Little-endian
Features View features

Processor

Cortex-M0+, 4 MHz

  • Timer
    16-Bit Timer with Input Capture, Output Compare and PWM 16-Bit Timer with Input Capture, Output Compare and PWM
    Watchdog Watchdog
  • Unknown
    16-Bit Analog to Digital Converter x 16-Bit Analog to Digital Converter
    Input and Output Ports x Input and Output Ports
    HSC Interface x HSC Interface
    I2C Interface x I2C Interface
    UART Interface x UART Interface