AppKit-E7-AIML
Gen 2
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Core
Cortex-M55
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Debug interfaces
J-Link
JTAG/SW
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Device
AE722F80F55D5LS -
CMSIS Pack
Ensemble
Overview of AK-E7-AIML HW:D3
The following picture shows the default board configuration.
On-board Debug Adapter
The board provides an on-board JLink debug-adapter with COM port routed to UART4. To enable the UART output configure the J15-A & J15-B to position U4.
